------------working and simulated----final-----------------------------------------
-- Company: 
-- Engineer: 		Sneha Nidhi
-- 
-- Create Date:    19:47:28 12/01/2010 
-- Design Name: 
-- Module Name:    ShiftRegister - Behavioral 
-- Project Name: 		RS232
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ShiftRegister is
    Port ( Reset : in  STD_LOGIC;
           Clk : in  STD_LOGIC;
           Enable : in  STD_LOGIC;--Permit to load and displ from rx232, active high sync
           D : in  STD_LOGIC;--data arrival--from rx 232
           Q : out  STD_LOGIC_VECTOR (7 downto 0)--Fifo_in--Byte received by the RS232 line to fifo
			);
end ShiftRegister;

architecture Behav of ShiftRegister is
signal temp_data :std_logic_vector(7 downto 0);

begin
process(Clk,Reset,Enable,D)
begin	
	if (Reset = '0') then
		temp_data <= "00000000";
	elsif (Clk' Event and Clk ='1' and Enable = '1') then
		temp_data(7)<= D;
		temp_data(6 downto 0)<= temp_data(7 downto 1);
	end if;  
end process;
Q(7)<= temp_data(7);
Q(6)<= temp_data(6);
Q(5)<= temp_data(5);			
Q(4)<= temp_data(4);
Q(3)<= temp_data(3);
Q(2)<= temp_data(2);
Q(1)<= temp_data(1);
Q(0)<= temp_data(0);
end Behav;

